1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a stacked-type semiconductor memory device (e.g., a multi-chip package [MCP] structure memory device) using a resistance-change memory element as a memory cell.
2. Description of the Related Art
It is essential to achieve a large capacity in development f memory devices such as flash memory. The memory devices have very important meanings to keep price competitiveness depending on in the following technique. According to the technique, a chip having the same memory capacity is realized using a smaller chip size.
A multi-chip package has been developed as a technique of relatively simple increasing the memory capacity of the same package. For example, in a multi-chip package structure memory device, a plurality of the same memory chips is stacked and packaged in one package.
The foregoing multi-chip package structure memory device has the following problem. Specifically, inherent chip addresses (row address, column address) must be given to a plurality of stacked memory chips. If not so, all memory chips make the same operation; as a result, there is no meaning of stacking memory chips.
The following technique is given as one course to solve the foregoing problem. According to the technique, each memory chip has a chip address identification pad. For example, bonding with respect to the foregoing pad is changed as “Chip ID [1:0]=┌Vss, Vss┘ or ┌Vss, Vdd┘” every memory chip. In this way, memory chip only corresponding to the chip address is selectable in each of a program (write) or read operation. Namely, a mutually different ID is assigned to the chip address identification pad of each memory chip.
Recently, development of a memory chip using a resistance-change memory element as a memory cell has been aggressively made (for example, see IEDM 2006 30. 8 “Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications”, VLSI Circuits 2007 p 186 “Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM”). The foregoing memory chip can execute a high-speed write operation as compared with a flash memory, and stacking is relatively easy. Considering the foregoing point, the memory chip has attracted much interest.
As described above, in the multi-chip package structure memory device, each memory chip of the package is identified by switching the bonding. However, the multi-chip package structure memory device must stack a plurality of memory chips in the package. In this case, the area and shape of the package are limited. Thus, preferably, each memory chip is stacked so that it is overlapped without shifting a position of each memory chip. In this case, short-circuit is made between pads of vertically overlapping memory chips, and thereby, there is no need to bond each memory chip; therefore, assembly is very easy. However, according to the foregoing technique, different ID is not set to the chip address identification pad of each memory chip. In other words, the same chip address is assigned to all the chip address identification pads of each memory chip. For this reason, there is a problem that it is impossible to identify each memory chip of the package.
Incidentally, a stacked-type semiconductor device capable of solving the foregoing problem has been already proposed (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2003-110086). However, the proposed stacked-type semiconductor device is applicable to a non-volatile memory chip such as NAND E2 PROM. Therefore, it is desired to provide a effective method of identifying each of a plurality of memory chips in the package in the multi-chip package structure memory device, which stacks a memory chip using a resistance-change memory element as a memory cell.